1. Field of the Invention
The present invention relates to a semiconductor memory capable of operating in burst mode and, more particularly, to a high-speed semiconductor memory used illustratively as a cache memory.
2. Description of the Related Art
There exist semiconductor memories capable of the so-called burst output. Such semiconductor memories include an address counter and a memory cell array. The address counter operates in response to a clock signal input. When read from memory cells in the memory cell array, the data is output in accordance with the result of the counting by the address counter.
FIG. 12 is a block diagram of a typical conventional SCRAM capable of operating in burst mode. Referring to FIG. 12, the SCRAM comprises a memory cell array 1, a decoder 2, a bit line pre charging circuit 3, a sense amplifier and write driver 4, registers 21 and 23, a read/write control circuit 22, and a burst counter unit 80.
The memory cell array 1 includes a plurality of memory cells MHC, MHC, etc., a plurality of word lines 11, 11, etc., and a plurality of bit line pairs 12, 12, etc. The memory cells MC, MC, etc. Constitute a matrix made of rows and columns, each cell accommodating data.
Each memory cell MC comprises two access transistors 13 and 14, two driver transistors 15 and 16, and two load resistors 17 and 18. The access transistors 13 and 14 and the driver transistors 15 and 16 are an n-channel MOS transistor each. The load resistors 17 and 18 are each composed of a resistance element, a p-channel MOS transistor or a thin film transistor.
The load resistor 17 and the driver transistor 15 are connected in series between a power supply node N1 that receives a supply potential and a grounding node N2 that receives a grounding potential. The load resistor 18 and the driver transistor 16 are also connected serially between the two nodes N1 and N2. The driver transistors 15 and 16 have their gate and drain electrodes connected by intersection.
The access transistor 13 has its gate electrode connected to a word line 11. The access transistor 13 is connected interposing between one of the two bit lines constituting a bit line pair 12, 12 on the one hand, and the connection node (storage node) between the load resistor 17 and the driver transistor 15 on the other hand.
The access transistor 14 has its gate electrode connected to the word line 11. The access transistor 14 is connected interposing between the other of the two bit lines constituting the bit line pair 12, 12 on the one hand, and the connection node (storage node) between the load resistor 18 and the driver transistor 16 on the other hand.
The word lines 11, 11, etc. Are each furnished to select the memory cells arranged thereon. The bit line pairs 12, 12, etc. Are each provided to transfer write and read data to and from the memory cell MC selected by the applicable word line 11.
An input pin 91 admits a clock signal CLK from the outside. An input pin 93 receives an advance signal ADV that is externally furnished. An input pin 94 receives an externally provided address strobe signal ADS. An input pin 100 admits an external address signal EXT.ADD from the outside. An input pin 101 gets a read/write control signal /WE furnished externally. The slash symbol (/) indicates that the signal having the symbol is an inverted signal. This applies throughout the description hereunder.
The burst counter unit 80 includes AND gates 81 and 82, a register 83 and a burst counter 84. The AND gate 81 receives the advance signal AD and clock signal CLK, and outputs a signal representing the result of the AND operation on the two signals. The AND gate 82 admits the address strobe signal ADS and clock signal CLK, and outputs a signal denoting the result of the AND operation on the two signals.
The register 83 receives both the output signal of the AND gate 82 and the external address signal EXT.ADD. In operation, the register 83 takes the external address signal EXT.ADD into the burst counter unit 80 in response to the output signal from the AND gate 82. The n-bit address admitted into the register 83 is separated into a k-bit address and an (n-k)-bit address.
The burst counter 84 is a binary counter that receives the output signals of the AND gates 81 and 82, and the k-bit address following the address separation. In operation, the burst counter 84 loads the k-bit address by responding to the output signal of the AND gate 82, and increments the value of the k-bit address in reply to the output signal of the AND gate 81.
The k-bit address representing the result of the counting by the burst counter 84 is then recombined with the separated (n-k)-bit address. The result is an n-bit internal address that is fed to the decoder 2. Given the n-bit internal address signal INT.ADD, the decoder 2 selects one word line 11.
The register 21 receives the clock signal CLK and the read/write control signal /WE. The read/write control signal /WE is admitted into the register 21 responding to a leading edge of the clock signal CLK. The read/write control signal /WE indicates a write state when brought Low, and denotes a read state when driven High. The read/write control circuit 22 outputs a control signal for controlling the bit line pre charging circuit 3 and the sense amplifier and write driver 4 in reply to the read/write control signal /WE admitted through the register 21.
Given the control signal from the read/write control circuit 22, the bit line precharging circuit 3 precharges a bit line pair 12, 12 to a predetermined high level in preparation for a read operation. Upon receipt of the control signal from the read/write control circuit 22, the sense amplifier and write driver 4 operates as follows:
In the write operation, the sense amplifier and write driver 4 transfers to the bit line pair 12, 12 the input data DI admitted into the register 23 from the outside via a data input/output pin 9.
The conventional SRAM of the above constitution typically works as follows: when the advance signal AD is brought High, the address on the burst counter 84 is incremented every time a leading edge of the clock signal CLK is encountered. As the internal address signal INT.ADD is incremented in this manner, the decoder 2 selects different word lines 11 successively.
Below is a description of how the SRAM of FIG. 12 works in a read operation. FIG. 13 is a timing chart showing typical waveforms of signals used by the SRAM of FIG. 12 in the read operation.
Referring to FIGS. 12 and 13, the read/write control signal /WE is fixed to the high level for the read operation. When a leading edge of the clock signal CLK is encountered, the address strobe signal ADS is brought High. This allows the external address input signal EXT.ADD to be admitted into the register 83.
Thereafter, every time the clock signal CLK is at a leading edge and the advance signal ADV is High, the address indicated by the internal address signal INT.ADD based on the address An given by the external address signal EXT.ADD is incremented by the burst counter 84. The incremented address occurs as An, An+1, An+2, etc.
This causes a different word line 11 to be selected in each cycle of the clock signal CLK. As a result, the output data DO varies in the sequence of Qn, Qn+1, Qn+2, etc. This in turn allows data to be output in burst mode from memory cells MC, MC, etc. In the memory cell array 1.
Below is a description of how the SRAM of FIG. 12 works in a write operation. FIG. 14 is a timing chart showing typical waveforms of signals used by the SRAM of FIG. 12 in the write operation.
Referring to FIGS. 12 and 14, the read/write control signal /WE for the write operation is given as a pulse signal as opposed to the high-level signal used in the read operation. The input data DI (Dn, Dn+1, Dn+2, etc.) Is admitted in synchronism with the pulse-type read/write control signal /WE.
In the write operation, the internal address INT.ADD based on the address An designated by the external address signal EXT.ADD varies in the same manner as in the read operation. This allows the input data DI to be written to memory cells MC, MC, etc. Of the memory cell array 1 in the sequence of Dn, Dn+1, Dn+2, etc.
What follows is a description of another conventional semiconductor memory capable of operating in burst mode. The description will center on the read circuit portion of the semiconductor memory.
FIG. 15 is a block diagram of one such conventional SRAM also capable of operating in burst mode. In FIG. 15, the common parts that also appear in FIG. 12 are designated by like reference numerals, and their descriptions are omitted hereunder where redundant.
The semiconductor memory of FIG. 15 differs from that of FIG. 12 in the following aspects: the burst counter unit 80 is not provided; an output register 5, a multiplexer 7, a burst counter unit 8 and an internal register 20 are furnished; and the memory cell array 1 is divided into a plurality of memory blocks M0 through M3.
The memory cell array 1 has a plurality of memory cells (like the memory cells MC, MC, etc. In FIG. 12) divided into a plurality of (e.g., four) memory blocks M0 through M3 in columns. In this case, the memory cell array 1 is divided into four memory blocks M0 through M3 illustratively of 72 bits each. In FIG. 15, a single unit of data is shown to be composed of 72 bits.
An input pin 90 receives a memory address input signal MADD for selecting one of the word lines 11 in the memory cell array 1. The internal register 20 admits the memory address signal MADD using an appropriate timing (e.g., in synchronism with the address strobe signal ADS) and sends the admitted address to the decoder 2 as an internal address signal INT.ADD.
In response to the internal address signal INT.ADD, the decoder 2 selects one of the word lines 11 in the memory cell array 1. A sense amplifier 41 in FIG. 15 is a latch type sense amplifier that constitutes part of the sense amplifier and write driver 4 in FIG. 12.
With the word line 11 selected, the sense amplifier 41 receives the data items read simultaneously from the memory blocks M0 through M3 over the bit lines (see FIG. 12). The sense amplifier 41 amplifies each of the data items thus received.
The output register 5 is composed of a plurality of D type flip-flop circuits each retaining the data item amplified by the sense amplifier 41. With this output register 5, the D type flip-flop circuits correspond to the memory blocks M0 through M3 in the memory cell array 1, serving as four data retaining blocks 50 through 53 respectively. Each of the data retaining blocks 50 through 53 in the output register 5 retains data in reply to a transfer signal TR.
An input pin 92 receives an external chunk address signal EXT.CHA for selecting one of the data retaining blocks 50 through 53 in the output register 5.
The burst counter unit 8 is identical in structure to the burst counter unit 80 in FIG. 12, except that the external address signal EXT.ADD of FIG. 12 is replaced by the external chunk address signal EXT.CHA. Thus the detailed structure of the burst counter unit 8 will not be discussed further.
Responding to the clock signal CLK, the burst counter unit 8 increments the value designated by the external chunk address signal EXT.CHA. The incremented result of the counting serves as an internal chunk address signal INT.CHA.
In reply to the internal chunk address signal INT.CHA, the multiplexer 7 selects and outputs one of the four 72-bit data items retained in the output register 5. That is, the multiplexer 7 selects one of the data retaining blocks 50 through 53 in the output register 5 by responding to the result of the counting by the burst counter unit 8.
Given the internal chunk address signal INT.CHA, the multiplexer 7 successively transfers to the data input/output pin 9 the four 72-bit data items retained in the data retaining blocks 50 through 53.
In the manner described, the SRAM of FIG. 15 performs the read operation in burst mode.
Below is a more detailed description of how the SRAM of FIG. 15 works in a read operation. FIG. 16 is a timing chart showing typical waveforms of signals used by the SRAM of FIG. 15 in the read operation. In FIG. 16, the cycles of the clock signal CLK are numbered 1, 2, 3, etc.
Referring to FIG. 16, the address An designated by the memory address signal MADD is admitted into the internal register 20 in response to the first leading edge in the second cycle of the clock signal CLK. With the address An thus admitted, the word line 11 (WL) becomes selectable between the second and the fourth cycle. In response to this, data is read from the memory cell array 1 and is amplified by the sense amplifier 41.
In the fourth cycle, the transfer signal TR is brought High for a predetermined period of time. In response, the sense amplifier 41 transfers the amplified data to each of the data retaining blocks 50 through 53 in the output register 5 while the fourth cycle is in effect.
In the fifth cycle, the burst counter unit 8 admits an address AC stemming from the external chunk address signal EXT.CHA. The counting by the burst counter unit 8 starts in the fifth cycle. Between the fifth and the eighth cycle, the internal chunk address signal INT.CHA varies in the sequence of Ac, Ac+1, Ac+2, etc.
Consequently, the data items held in the data retaining blocks 50 through 53 of the output register 5 are output successively from the multiplexer 7 to the outside via the data input/output pin 9.
As described, the output data DO is output in burst mode, i.e., in the sequence of D(An), D(An+1), etc., from the fifth through the eighth cycle.
Data is then read from an address Am that is input as the memory address signal MADD following the address An. In this case, the data corresponding to the address Am is read in the same manner as the data corresponding to the address An.
While the data related to the current address An is under way, it is necessary to retain, in the data retaining blocks 50 through 53 of the output register 5, the data associated with the address An. For this reason, the transfer signal TR for reading the data corresponding to the next address Am is driven High in the ninth cycle following the completion of the burst output of the data associated with the current address An.
Therefore, the burst output of the output data DO related to the next address Am is carried out one cycle after the end of the burst output concerning the current address An, as shown in the sequence of D(Am), D(Am+1), etc. In this manner, the SRAM of FIG. 15 also allows the data therein to be read out in burst mode.
The conventional SRAMs outlined above have some disadvantages that will now be described.
With the conventional SRAM of FIG. 12, a word line 11 is selected and the related parts of the memory cell array 1 are activated in each of the cycles of the furnished clock signal CLK. It follows that the clock cycle time defining a period in which to repeat data output (called the data transfer called hereunder) is determined by the delay times in operations of the word lines 11, 11, etc., of the bit line pairs 12, 12, etc., and of the memory cell arrays MC, MC, etc.
This means that, with the SRAM of FIG. 12, attempts to reduce the cycle time of the clock signal CLK for higher operating speeds fail to make the cycle time shorter than the sum of the operative delays resulting from the parts of the memory cell array 1. Such delays in the operations of various parts in the memory cell array 1 prevent the SRAM of FIG. 12 from operating more quickly than at present.
With the SRAM of FIG. 15, the timing for the burst output of data is irrelevant to the operative delays of the various parts in the memory cell array 1. Such delays do not hamper efforts to make the memory as a whole operate at higher speeds than before. However, as mentioned above, the burst output of the data read from the memory cell array 1 poses a different problem.
That is, a data-free period (an interruption in the flow of data output) is bound to occur between two burst outputs, one relating to the current memory address An, the other associated with the next memory address Am.
Suppose that a data output interruption of one cycle period occurs following each burst output lasting four cycles. In that case, if one burst output is taken as a single period, the data transfer period is prolonged by 20 percent. In other words, the data transfer rate declines by 20 percent.
Thus although the SRAM of FIG. 15 is exempt from the operative delays in the parts of the memory cell array 1, the memory fails to shorten sufficiently the data transfer period in enhancing its operation speed. As a result, the SRAM of FIG. 15 is incapable of operating at a sufficiently high speed.